This patent document relates generally to the self-testing of memory, and in particular to self-testing and reusing of reference cells in a memory architecture, such as an embedded MRAM memory in an artificial intelligence chip.
Memory is an important component in an artificial intelligence (AI) chip that has low power and high performance characteristics as each AI engine is usually comprised of multiple memory components. Conventional tests for memories such as, static random access memory (SRAM) or magnetoresistive random access memory (MRAM), typically use built-in self-test/repair (BIST/R) methods to perform memory bit quality verification and repair functions. For example, Benso et al. propose a built-in self-repair (BISR) structure for RAM cores. See Benso, Chiusano, Di Natale and Prinetto, “An On-Line BIST RAM Architecture with Self-Repair Capabilities,” IEEE Transactions on Reliability, Vol 51, No. 1, March 2002. BIST/R methods are usually performed at wafer level, which requires critical path of content addressable memory (CAM), controller, register array and proper encoding logic inside the chip. This approach takes much space inside the chip as it requires the insertion of redundant columns/rows/cell arrays and architectural structures.
In an MRAM memory architecture, self-testing is traditionally performed using reference cells built inside the memory architecture to ensure sensing margin due to process voltage temperature (PVT) change such that the stored information of 0 and 1 can be sensed well. For example, Na et al. describe three types of reference cells/units in a spin transfer torque (STT)-RAM architecture: reference column, reference row and reference array. See Na, Kim, Kim, Kang and Jung, “Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM,” IEEE Transactions on Circuits and Systems, Vol. 61, No. 12, December 2014. The reference cells in an MRAM memory are generally used in the reading process, in which the resistances of the storage cells will be measured and compared to those of the reference cells to decide whether a ‘1’ or ‘0’ is stored in each of the storage cells correctly. Reference cells can be built just like storage cells, but are preset or programmed at known states, such as 1 's or 0's. Reference cells can be programmed at the factory test stage. A memory self-test that uses reference cells needs to take into account which reference cell unit, such as a reference row, reference column or reference array, is bad. If reference columns are used, and if one or more cells in a reference column are bad, that reference column will be replaced by a redundant column. This approach often requires more redundant reference cells in order to achieve better chip performance. However, this increases the chip size. Testing may be done at either wafer or chip packaging level or both. Like conventional testing in a memory, reference cells cannot be altered once the chip is fabricated.
As described above, existing approaches are particularly of challenge when applied to a low power and high performance AI chip with embedded MRAM memory that has large memory bits but requires small chip size. This challenge becomes critically important when designing an AI chip for mobile devices. Further, redundant cells as with conventional BIST/R processes or reference cells in an MRAM memory are fixed and cannot be changed or reused once the chip is fabricated. Furthermore, self-testing is usually done at wafer level and can be time consuming.